H8S2245 datasheet(758/818 Pages) RENESAS

758 / 818 page

Appendix B Register Field

Rev.3.00 Mar. 26, 2007 Page 716 of 772

REJ09B0355-0300

TSR0—Timer Status Register 0

H'FFD5

TPU0

—

TCFV

R/(W)*1

TGFD

R/(W)*1

TGFA

R/(W)*1

TGFC

R/(W)*1

TGFB

R/(W)*1

Notes: 1. Can only be written with 0 for flag clearing.

2. DTC can clear this bit only when DISEL is 0 with the transfer counter not being 0.

Overflow Flag

TGRD·Input Capture/Output Compare Flag

TGRC·Input Capture/Output Compare Flag

TGRB·Input Capture/Output Compare Flag

[Clearing conditions]

• When DTC*2 is activated by TGIA interrupt

while DISEL bit of MRB in DTC is 0.

• When 0 is written to TGFA after reading

TGFA = 1

TGRA·Input Capture/Output Compare Flag

Bit

Initial value

Read/Write

[Setting conditions]

• When TCNT = TGRA while TGRA is function-

ing as output compare register

• When TCNT value is transferred to TGRA by

input capture signal while TGRA is functioning

as input capture register

[Clearing conditions]

• When DTC*2 is activated by TGIB interrupt while DISEL

bit of MRB in DTC is 0.

• When 0 is written to TGFB after reading TGFB = 1

[Setting conditions]

• When TCNT = TGRB while TGRB is functioning as

output compare register

• When TCNT value is transferred to TGRB by input

capture signal while TGRB is functioning as input

capture register

[Clearing conditions]

• When DTC*2 is activated by TGIC interrupt while DISEL bit of MRB in

DTC is 0

• When 0 is written to TGFC after reading TGFC = 1

[Setting conditions]

• When TCNT = TGRC while TGRC is functioning as output compare

• When TCNT value is transferred to TGRC by input capture signal

while TGRC is functioning as input capture register

[Clearing conditions]

• When DTC*2 is activated by TGID interrupt while DISEL bit of MRB in DTC

is 0

• When 0 is written to TGFD after reading TGFD = 1

[Setting conditions]

• When TCNT = TGRD while TGRD is functioning as output compare register

• When TCNT value is transferred to TGRD by input capture signal while

TGRD is functioning as input capture register

[Clearing condition]

When 0 is written to TCFV after reading TCFV = 1

[Setting condition]

When the TCNT value overflows (changes from H'FFFF to H'0000 )

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