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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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H8S2245 데이터시트(PDF) 754 Page - Renesas Technology Corp |
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H8S2245 데이터시트(HTML) 754 Page - Renesas Technology Corp |
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754 / 818 page  Appendix B Register Field Rev.3.00 Mar. 26, 2007 Page 712 of 772 REJ09B0355-0300 TMDR0—Timer Mode Register 0 H'FFD1 TPU0 7 — 1 — 6 — 1 — 5 BFB 0 R/W 4 BFA 0 R/W 3 MD3 0 R/W 0 MD0 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 1 Buffer Operation Setting B TGRB operates normally 0 1 Buffer Operation Setting A TGRA operates normally 0 1 Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 — Mode 0 1 * 0 1 0 1 * 0 1 0 1 0 1 0 1 * Notes: 1. 2. MD3 is a reserved bit. In a write, it should always be written with 0. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always be written to MD2. Legend: *: Don't care Bit Initial value Read/Write : : : TGRA and TGRC used together for buffer operation TGRB and TGRD used together for buffer operation |
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