HD6432351 datasheet(429/1025 Pages) RENESAS

429 / 1025 page

Section 9 I/O Ports

Rev. 3.00 Sep 15, 2006 page 395 of 988

REJ09B0330-0300

Port E Data Register (PEDR)

PE7DR

R/W

PE6DR

R/W

PE5DR

R/W

PE4DR

R/W

PE3DR

R/W

PE0DR

R/W

PE2DR

R/W

PE1DR

R/W

Bit

Initial value

R/W

PEDR is an 8-bit readable/writable register that stores output data for the port E pins (PE7 to PE0).

PEDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior

state after a manual reset, and in software standby mode.

Port E Register (PORTE)

PE7

—*

PE6

—*

PE5

—*

PE4

—*

PE3

—*

PE0

—*

PE2

—*

PE1

—*

Bit

Initial value

R/W

Note: * Determined by state of pins PE7 to PE0.

PORTE is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of

output data for the port E pins (PE7 to PE0) must always be performed on PEDR.

If a port E read is performed while PEDDR bits are set to 1, the PEDR values are read. If a port E

read is performed while PEDDR bits are cleared to 0, the pin states are read.

After a power-on reset and in hardware standby mode, PORTE contents are determined by the pin

states, as PEDDR and PEDR are initialized. PORTE retains its prior state after a manual reset, and

in software standby mode.

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