HD6432351 datasheet(95/1025 Pages) RENESAS

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Section 2 CPU

Rev. 3.00 Sep 15, 2006 page 61 of 988

REJ09B0330-0300

2.8.3

Exception-Handling State

The exception-handling state is a transient state that occurs when the CPU alters the normal

processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address

(vector) from the exception vector table and branches to that address.

(1) Types of Exception Handling and Their Priority

Exception handling is performed for traces, resets, interrupts, and trap instructions. Table 2.7

indicates the types of exception handling and their priority. Trap instruction exception handling is

always accepted, in the program execution state.

Exception handling and the stack structure depend on the interrupt control mode set in SYSCR.

Table 2.7

Exception Handling Types and Priority

Priority

Type of Exception

Detection Timing

Start of Exception Handling

High

Reset

Synchronized with clock

Exception handling starts

immediately after a low-to-high

transition at the

RES pin, or

when the watchdog timer

overflows.

Trace

End of instruction

execution or end of

exception-handling

sequence*

When the trace (T) bit is set to

1, the trace starts at the end of

the current instruction or current

exception-handling sequence

Interrupt

End of instruction

execution or end of

exception-handling

sequence*

When an interrupt is requested,

exception handling starts at the

end of the current instruction or

current exception-handling

sequence

Low

Trap instruction

When TRAPA instruction

is executed

Exception handling starts when

a trap (TRAPA) instruction is

executed*

Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception-handling is not

executed at the end of the RTE instruction.

2. Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions,

or immediately after reset exception handling.

3. Trap instruction exception handling is always accepted, in the program execution state.

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