HD6432351 datasheet(72/1025 Pages) RENESAS

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Section 2 CPU

Rev. 3.00 Sep 15, 2006 page 38 of 988

REJ09B0330-0300

2.6

Instruction Set

2.6.1

Overview

The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in

table 2.1.

Table 2.1

Instruction Classification

Function

Instructions

Size

Types

Data transfer

MOV

BWL 5

POP*

1, PUSH*1

LDM, STM

MOVFPE, MOVTPE*

ADD, SUB, CMP, NEG

BWL 19

Arithmetic

operations

ADDX, SUBX, DAA, DAS

INC, DEC

BWL

ADDS, SUBS

MULXU, DIVXU, MULXS, DIVXS

EXTU, EXTS

TAS

Logic operations

AND, OR, XOR, NOT

BWL 4

Shift

SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR

BWL 8

Bit manipulation

BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND,

BIAND, BOR, BIOR, BXOR, BIXOR

Branch

Bcc*

2, JMP, BSR, JSR, RTS

—

System control

TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP —

Block data transfer EEPMOV

—

Legend: B: Byte

W: Word

Longword

Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn,

@-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L

ERn, @-SP.

2. Bcc is the general name for conditional branch instructions.

3. Cannot be used in the H8S/2350 Group.

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