HD6432351 datasheet(16/1025 Pages) RENESAS

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Rev. 3.00 Sep 15, 2006 page xvi of xxxiv

Item

Page

Revision (See Manual for Details)

B.2 Functions

846

Figure amended

BCRL H'FED5 Bus Controller

DACK Timing Select

When DMAC single address transfer is performed in

DRAM space, full access is always executed

DACK

signal goes low from Tr or T1 cycle

Burst access is possible when DMAC single address

transfer is performed in DRAM space

DACK signal

goes low from Tc1 or T2 cycle

923

Figure amended

TMDR1 H'FFE1 TPU1

(Before) 1 Phase counting mode 4

→ (After) Phase counting

mode 4

924

Figure amended

TIORL H'FFE2 TPU1

TGR1B I/O Control

Legend: *: Don’t care

TGR1B

is output

compare

Output disabled

0 output at compare match

1 output at compare match

Toggle output at compare match

0 output at compare match

1 output at compare match

Toggle output at compare match

Input capture at rising edge

Input capture at falling edge

Input capture at both edges

Initial output is

0 output

TGR1B

is input

capture

Output disabled

Initial output is

1 output

Capture input

source is

TIOCB1 pin

Capture input

source is TGR0B

compare match/

input capture

Input capture at generation of

TGR0B compare match/input

capture

C.13 Port G Block

Diagram

Figure C.13 (c-2)

H8S/2350 Port G Block

Diagram (Pin PG4)

975

Figure C.13 (c-2) amended

Mode 1/2/4/5/6

980

Description in MCU operating mode in table D.2 amended

Port D 1, 4, 5

981

PF0/BREQ 1, 4, 5

D.2 Port States in Each

Mode [H8S/2350]

Table D.2 I/O Port

States in Each

Processing State

(H8S/2350)

982

PG0/CAS (Before) 1 to 3, 7 → (After) 1

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