HD6432351 datasheet(437/1025 Pages) RENESAS

437 / 1025 page

Section 9 I/O Ports

Rev. 3.00 Sep 15, 2006 page 403 of 988

REJ09B0330-0300

Selection Method and Pin Functions

PF3/LWR

The pin function is switched as shown below according to the operating mode

and bit PF3DDR.

Operating

Mode

Modes 1, 2, 4 to 6*

Modes 3 and 7*

PF3DDR

—

Pin function

LWR output pin

PF3 input pin

PF3 output pin

PF2/LCAS/WAIT/

BREQO

The pin function is switched as shown below according to the combination of

the operating mode, and bits RMTS2 to RMTS0, LCASS, BREQOE, WAITE,

ABW5 to ABW2, and PF2DDR.

Operating

Mode

Modes 1, 2, 4 to 6*

Modes 3 and 7*

LCASS

—

BREQOE

—

WAITE

—

PF2DDR

—

Pin function

PF2

input

PF2

output

WAIT

input

BREQO

output

LCAS

output

PF2

input

PF2

output

Note:

1. Only in DRAM space 16-bit access in modes 4 to 6 when RMTS2

to RMTS0 = B'001 to B'011.

PF1/BACK

The pin function is switched as shown below according to the combination of

the operating mode, and bits BRLE and PF1DDR.

Operating

Mode

Modes 1, 2, 4 to 6*

Modes 3 and 7*

BRLE

—

PF1DDR

—

Pin function

PF1

input pin

PF1

output pin

BACK

output pin

PF1

input pin

PF1

output pin

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