HD6432351 datasheet(463/1025 Pages) RENESAS

463 / 1025 page

Section 10 16-Bit Timer Pulse Unit (TPU)

Rev. 3.00 Sep 15, 2006 page 429 of 988

REJ09B0330-0300

Channel

Bit 7

IOD3

Bit 6

IOD2

Bit 5

IOD1

Bit 4

IOD0 Description

Output disabled

(Initial value)

0 output at compare match

1 output at compare match

TGR0D

is output

compare

Initial output is 0

output

Toggle output at compare

match

Output disabled

0 output at compare match

1 output at compare match

Initial output is 1

output

Toggle output at compare

match

Input capture at rising edge

Input capture at falling edge

Capture input

source is

TIOCD0 pin

Input capture at both edges

TGR0D

is input

capture

Capture input

source is channel

1/count clock

Input capture at TCNT1

count-up/count-down*

Legend: *: Don’t care

Notes: 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and

φ/1 is used as the TCNT1

count clock, this setting is invalid and input capture is not generated.

2. When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register, this

setting is invalid and input capture/output compare is not generated.

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