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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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HD6432351 데이터시트(PDF) 567 Page - Renesas Technology Corp |
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HD6432351 데이터시트(HTML) 567 Page - Renesas Technology Corp |
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567 / 1025 page  Section 12 Watchdog Timer (WDT) Rev. 3.00 Sep 15, 2006 page 533 of 988 REJ09B0330-0300 12.1.3 Pin Configuration Table 12.1 describes the WDT output pin. Table 12.1 WDT Pin Name Symbol I/O Function Watchdog timer overflow WDTOVF Output Outputs counter overflow signal in watchdog timer mode 12.1.4 Register Configuration The WDT has three registers, as summarized in table 12.2. These registers control clock selection, WDT mode switching, and the reset signal. Table 12.2 WDT Registers Address* 1 Name Abbreviation R/W Initial Value Write* 2 Read Timer control/status register TCSR R/(W)* 3 H'18 H'FFBC H'FFBC Timer counter TCNT R/W H'00 H'FFBC H'FFBD Reset control/status register RSTCSR R/(W)* 3 H'1F H'FFBE H'FFBF Notes: 1. Lower 16 bits of the address. 2. For details of write operations, see section 12.2.4, Notes on Register Access. 3. Only a write of 0 is permitted to bit 7, to clear the flag. |
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