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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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HD6432351 데이터시트(PDF) 577 Page - Renesas Technology Corp |
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HD6432351 데이터시트(HTML) 577 Page - Renesas Technology Corp |
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577 / 1025 page  Section 12 Watchdog Timer (WDT) Rev. 3.00 Sep 15, 2006 page 543 of 988 REJ09B0330-0300 12.4 Interrupts During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. 12.5 Usage Notes 12.5.1 Contention between Timer Counter (TCNT) Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 12.8 shows this operation. Address φ Internal write signal TCNT input clock TCNT NM T1 T2 TCNT write cycle Counter write data Figure 12.8 Contention between TCNT Write and Increment |
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