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HD6432351 데이터시트(PDF) 656 Page - Renesas Technology Corp |
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HD6432351 데이터시트(HTML) 656 Page - Renesas Technology Corp |
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656 / 1025 page ![]() Section 14 Smart Card Interface Rev. 3.00 Sep 15, 2006 page 622 of 988 REJ09B0330-0300 14.3.3 Data Format Figure 14.3 shows the Smart Card interface data format. In reception in this mode, a parity check is carried out on each frame, and if an error is detected an error signal is sent back to the transmitting end, and retransmission of the data is requested. If an error signal is sampled during transmission, the same data is retransmitted. Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp When there is no parity error Transmitting station output Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp When a parity error occurs Transmitting station output DE Receiving station output : Start bit : Data bits : Parity bit : Error signal Legend: Ds D0 to D7 Dp DE Figure 14.3 Smart Card Interface Data Format The operation sequence is as follows. [1] When the data line is not in use it is in the high-impedance state, and is fixed high with a pull- up resistor. [2] The transmitting station starts transfer of one frame of data. The data frame starts with a start bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp). [3] With the Smart Card interface, the data line then returns to the high-impedance state. The data line is pulled high with a pull-up resistor. |
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