 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
HD6432351 데이터시트(PDF) 711 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
HD6432351 데이터시트(HTML) 711 Page - Renesas Technology Corp |
|
|
711 / 1025 page  Section 19 Clock Pulse Generator Rev. 3.00 Sep 15, 2006 page 677 of 988 REJ09B0330-0300 Section 19 Clock Pulse Generator 19.1 Overview The H8S/2350 Group has a built-in clock pulse generator (CPG) that generates the system clock ( φ), the bus master clock, and internal clocks. The clock pulse generator consists of an oscillator circuit, a duty adjustment circuit, a medium- speed clock divider, and a bus master clock selection circuit. 19.1.1 Block Diagram Figure 19.1 shows a block diagram of the clock pulse generator. EXTAL XTAL Duty adjustment circuit Oscillator Medium- speed divider System clock to φ pin Internal clock to supporting modules Bus master clock to CPU, DTC, and DMAC φ/2 to φ/32 SCK2 to SCK0 SCKCR Bus master clock selection circuit Figure 19.1 Block Diagram of Clock Pulse Generator |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
