HD6432351 datasheet(880/1025 Pages) RENESAS

880 / 1025 page

Appendix B Internal I/O Register

Rev. 3.00 Sep 15, 2006 page 846 of 988

REJ09B0330-0300

BCRL—Bus Control Register L

H'FED5

Bus Controller

BRLE

R/W

BREQOE

R/W



R/W

LCASS

R/W

DDS

R/W

WAITE

R/W



R/W

WDBE

R/W

Bit

Initial value

Read/Write

Bus Release Enable

External bus release is disabled

External bus release is enabled

BREQO Pin Enable

BREQO output disabled

BREQO output enabled

Reserved

Only 1 should be written to this bit

Reserved

Only 0 should be written to this bit

Write Data Buffer Enable

WAIT Pin Enable

Wait input by

WAIT

pin disabled

Wait input by

WAIT

pin enabled

Write data buffer

function not used

Write data buffer

function used

LCAS Select

Write 0 to this bit when using the DRAM interface

DACK Timing Select

When DMAC single address transfer is performed in

DRAM space, full access is always executed

DACK

signal goes low from Tr or T1 cycle

Burst access is possible when DMAC single address

transfer is performed in DRAM space

DACK signal

goes low from Tc1 or T2 cycle

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