HD6432351 datasheet(890/1025 Pages) RENESAS

890 / 1025 page

Appendix B Internal I/O Register

Rev. 3.00 Sep 15, 2006 page 856 of 988

REJ09B0330-0300

DMAWER—DMA Write Enable Register

H'FF00

DMAC

—

WE1B

R/W

WE0A

R/W

WE1A

R/W

WE0B

R/W

Bit

DMAWER

Initial value

Read/Write

Write Enable 1B

Write Enable 1A

Writes to all bits in DMACR0A,

and bits 8, 4, and 0 in DMABCR

are disabled

Write Enable 0A

Write Enable 0B

Writes to all bits in DMACR0A,

and bits 8, 4, and 0 in DMABCR

are enabled

Writes to all bits in DMACR0B, bits 9,

5, and 1 in DMABCR, and bit 4 in

DMATCR are disabled

Writes to all bits in DMACR0B, bits 9,

5, and 1 in DMABCR, and bit 4 in

DMATCR are enabled

Writes to all bits in DMACR1A, and bits

10, 6, and 2 in DMABCR are disabled

Writes to all bits in DMACR1A, and bits

10, 6, and 2 in DMABCR are enabled

Writes to all bits in DMACR1B, bits 11, 7, and 3 in

DMABCR, and bit 5 in DMATCR are disabled

Writes to all bits in DMACR1B, bits 11, 7, and 3 in

DMABCR, and bit 5 in DMATCR are enabled

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