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HD6432351 데이터시트(PDF) 895 Page - Renesas Technology Corp |
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HD6432351 데이터시트(HTML) 895 Page - Renesas Technology Corp |
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895 / 1025 page ![]() Appendix B Internal I/O Register Rev. 3.00 Sep 15, 2006 page 861 of 988 REJ09B0330-0300 DMABCRH—DMA Band Control Register H'FF06 DMAC DMABCRL—DMA Band Control Register H'FF07 DMAC 15 FAE1 0 R/W 14 FAE0 0 R/W 13 — 0 R/W 12 — 0 R/W 11 DTA1 0 R/W 8 — 0 R/W 10 — 0 R/W 9 DTA0 0 R/W Full address mode Bit DMABCRH Initial value Read/Write : : : : 0 1 Short address mode Full address mode Channel 1 Full Address Enable 0 1 Short address mode Full address mode Channel 0 Full Address Enable 0 Clearing of selected internal interrupt source at time of DMA transfer is disabled Channel 1 Data Transfer Acknowledge 1 Clearing of selected internal interrupt source at time of DMA transfer is enabled 0 Clearing of selected internal interrupt source at time of DMA transfer is disabled Channel 0 Data Transfer Acknowledge 1 Clearing of selected internal interrupt source at time of DMA transfer is enabled (Continued on next page) |
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