| 전자부품 데이터시트 검색엔진 |
|
HD6432351 데이터시트(PDF) 952 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
HD6432351 데이터시트(HTML) 952 Page - Renesas Technology Corp |
|
952 / 1025 page ![]() Appendix B Internal I/O Register Rev. 3.00 Sep 15, 2006 page 918 of 988 REJ09B0330-0300 TIOR0L—Timer I/O Control Register 0L H'FFD3 TPU0 0 1 TGR0D I/O Control 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * 0 1 TGR0C I/O Control 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * Legend: *: Don’t care Notes: Note: When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register, this setting is invalid and input capture/output compare is not generated. 7 IOD3 0 R/W 6 IOD2 0 R/W 5 IOD1 0 R/W 4 IOD0 0 R/W 3 IOC3 0 R/W 0 IOC0 0 R/W 2 IOC2 0 R/W 1 IOC1 0 R/W Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. Bit Initial value Read/Write : : : : TGR0C is output compare register Output disabled 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Initial output is 0 output TGR0C is input capture register Output disabled Initial output is 1 output Capture input source is TIOCC0 pin Capture input source is channel 1/count clock Input capture at TCNT1 count-up/ count-down TGR0D is output compare register Output disabled 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Initial output is 0 output TGR0D is input capture register*2 Output disabled Initial output is 1 output Capture input source is TIOCD0 pin Capture input source is channel 1/count clock Input capture at TCNT1 count-up/ count-down*1 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000, and φ/1 is used as the TCNT1 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register, this setting is invalid and input capture/output compare is not generated. Legend: *: Don’t care |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |