HD6432351 datasheet(129/1025 Pages) RENESAS

129 / 1025 page

Section 5 Interrupt Controller

Rev. 3.00 Sep 15, 2006 page 95 of 988

REJ09B0330-0300

5.2.2

Interrupt Priority Registers A to K (IPRA to IPRK)

—

IPR6

R/W

IPR5

R/W

IPR4

R/W

—

IPR0

R/W

IPR2

R/W

IPR1

R/W

Bit

Initial value

R/W

The IPR registers are eleven 8-bit readable/writable registers that set priorities (levels 7 to 0) for

interrupts other than NMI.

The correspondence between IPR settings and interrupt sources is shown in table 5.3.

The IPR registers set a priority (level 7 to 0) for each interrupt source other than NMI.

The IPR registers are initialized to H'77 by a reset and in hardware standby mode.

Bits 7 and 3—Reserved: Read-only bits, always read as 0.

Table 5.3

Correspondence between Interrupt Sources and IPR Settings

Bits

6 to 4

2 to 0

IPRA

IRQ0

IRQ1

IPRB

IRQ2

IRQ3

IRQ4

IRQ5

IPRC

IRQ6

IRQ7

DTC

IPRD

Watchdog timer

Refresh timer

IPRE

—*

A/D converter

IPRF

TPU channel 0

TPU channel 1

IPRG

TPU channel 2

TPU channel 3

IPRH

TPU channel 4

TPU channel 5

IPRI

—*

IPRJ

DMAC

SCI channel 0

IPRK

SCI channel 1

—*

Note:

* Reserved bits. These bits cannot be modified and are always read as 1.

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