HD6432351 datasheet(172/1025 Pages) RENESAS

172 / 1025 page

Section 6 Bus Controller

Rev. 3.00 Sep 15, 2006 page 138 of 988

REJ09B0330-0300

Bits 1 and 0—Refresh Cycle Wait Control 1 and 0 (RLW1, RLW0): These bits select the

number of wait states to be inserted in a DRAM interface CAS-before-RAS refresh cycle. This

setting is used for all areas designated as DRAM space. Wait input by the

WAIT pin is disabled.

Bit 1

RLW1

Bit 0

RLW0

Description

No wait state inserted

(Initial value)

1 wait state inserted

2 wait states inserted

3 wait states inserted

6.2.7

DRAM Control Register (DRAMCR)

RFSHE

R/W

RCW

R/W

RMODE

R/W

CMF

R/W

CMIE

R/W

CKS0

R/W

CKS2

R/W

CKS1

R/W

Bit

Initial value

R/W

DRAMCR is an 8-bit readable/writable register that selects the DRAM refresh mode and refresh

counter clock, and controls the refresh timer.

DRAMCR is initialized to H'00 by a power-on reset and in hardware standby mode. It is not

initialized by a manual reset or in software standby mode.

Bit 7—Refresh Control (RFSHE): Selects whether or not refresh control is performed. When

refresh control is not performed, the refresh timer can be used as an interval timer. Refresh control

is not performed in normal mode.

Bit 7

RFSHE

Description

Refresh control is not performed

(Initial value)

Refresh control is performed

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