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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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HD6432351 데이터시트(PDF) 195 Page - Renesas Technology Corp |
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HD6432351 데이터시트(HTML) 195 Page - Renesas Technology Corp |
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195 / 1025 page  Section 6 Bus Controller Rev. 3.00 Sep 15, 2006 page 161 of 988 REJ09B0330-0300 6.5 DRAM Interface 6.5.1 Overview When the H8S/2350 Group is in advanced mode, external space areas 2 to 5 can be designated as DRAM space, and DRAM interfacing performed. With the DRAM interface, DRAM can be directly connected to the H8S/2350 Group. A DRAM space of 2, 4, or 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in BCRH. Burst operation is also possible, using fast page mode. 6.5.2 Setting DRAM Space Areas 2 to 5 are designated as DRAM space by setting bits RMTS2 to RMTS0 in BCRH. The relation between the settings of bits RMTS2 to RMTS0 and DRAM space is shown in table 6.5. Possible DRAM space settings are: one area (area 2), two areas (areas 2 and 3), and four areas (areas 2 to 5). Table 6.5 Settings of Bits RMTS2 to RMTS0 and Corresponding DRAM Spaces RMTS2 RMTS1 RMTS0 Area 5 Area 4 Area 3 Area 2 0 1 Normal space DRAM space 0 Normal space DRAM space 0 1 1 DRAM space |
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