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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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HD6432351 데이터시트(PDF) 209 Page - Renesas Technology Corp |
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HD6432351 데이터시트(HTML) 209 Page - Renesas Technology Corp |
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209 / 1025 page  Section 6 Bus Controller Rev. 3.00 Sep 15, 2006 page 175 of 988 REJ09B0330-0300 (2) Self-Refreshing A self-refresh mode (battery backup mode) is provided for DRAM as a kind of standby mode. In this mode, refresh timing and refresh addresses are generated within the DRAM. To select self-refreshing, set the RFSHE bit and RMODE bit in DRAMCR to 1. Then, when a SLEEP instruction is executed to enter software standby mode, the CAS and RAS signals are output and DRAM enters self-refresh mode, as shown in figure 6.27. When software standby mode is exited, the RMODE bit is cleared to 0 and self-refresh mode is cleared. When switching to software standby mode, if there is a CBR refresh request, CBR refreshing is executed before self-refresh mode is entered. TRp φ CSn (RAS) TRcr CAS, LCAS HWR (WE) TRc3 Software standby Note: n = 2 to 5 High Figure 6.27 Self-Refresh Timing (When CW2 = 1, or CW2 = 0 and LCASS = 0) |
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