HD6432351 datasheet(224/1025 Pages) RENESAS

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Section 6 Bus Controller

Rev. 3.00 Sep 15, 2006 page 190 of 988

REJ09B0330-0300

6.10.4

Transition Timing

Figure 6.37 shows the timing for transition to the bus-released state.

CPU

cycle

External bus released state

CPU cycle

Address

Minimum

1 state

Address bus

Data bus

HWR, LWR

BREQ

BACK

High impedance

[1]

[2]

[3]

[4]

[5]

[1]

[2]

[3]

[4]

[5]

Low level of

BREQ pin is sampled at rise of T

2 state.

BACK pin is driven low at end of CPU read cycle, releasing bus to external bus master.

BREQ pin state is still sampled in external bus released state.

High level of

BREQ pin is sampled.

BACK pin is driven high, ending bus release cycle.

High impedance

Figure 6.37 Bus-Released State Transition Timing

6.10.5

Usage Note

When MSTPCR is set to H'FFFF or H'EFFF and a transition is made to sleep mode, the external

bus release function halts. Therefore, MSTPCR should not be set to H'FFFF or H'EFFF if the

external bus release function is to be used in sleep mode.

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