HD6432351 datasheet(290/1025 Pages) RENESAS

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HD6432351 데이터시트(PDF) 290 Page - Renesas Technology Corp

부품명	HD6432351

상세설명	16-Bit Single-Chip Microcomputer

PDF	1025 Pages

Scroll/Zoom	100%

제조업체	RENESAS [Renesas Technology Corp]

홈페이지	http://www.renesas.com

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290 / 1025 page

Section 7 DMA Controller (DMAC)

Rev. 3.00 Sep 15, 2006 page 256 of 988

REJ09B0330-0300

ETCRAL is decremented by 1 each time a byte or word transfer is performed. In response to a

single transfer request, burst transfer is performed until the value in ETCRAL reaches H'00.

ETCRAL is then loaded with the value in ETCRAH. At this time, the value in the MAR register

for which a block designation has been given by the BLKDIR bit in DMACRA is restored in

accordance with the DTSZ, SAID/DAID, and SAIDE/DAIDE bits in DMACR.

ETCRB is decremented by 1 every block transfer, and when the count reaches H'0000 the DTE bit

is cleared and transfer ends. If the DTIE bit is set to 1 at this point, an interrupt request is sent to

the CPU or DTC.

Figure 7.15 shows the operation flow in block transfer mode.

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