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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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HD64F2149YV 데이터시트(PDF) 395 Page - Renesas Technology Corp |
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HD64F2149YV 데이터시트(HTML) 395 Page - Renesas Technology Corp |
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395 / 1075 page  Section 12 8-Bit Timers Rev. 3.00 Jan 18, 2006 page 367 of 1044 REJ09B0280-0300 φ External clock input pin TCNT input clock TCNT N – 1 N N + 1 Figure 12.3 Count Timing for External Clock Input 12.3.2 Compare-Match Timing Setting of Compare-Match Flags A and B (CMFA, CMFB): The CMFA and CMFB flags in TCSR are set to 1 by a compare-match signal generated when the TCOR and TCNT values match. The compare-match signal is generated at the last state in which the match is true, just before the timer counter is updated. Therefore, when TCOR and TCNT match, the compare-match signal is not generated until the next incrementation clock input. Figure 12.4 shows this timing. φ TCNT N N + 1 TCOR N Compare-match signal CMF Figure 12.4 Timing of CMF Setting |
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