HD64F2149YV datasheet(435/1075 Pages) RENESAS

435 / 1075 page

Section 13 Timer Connection

Rev. 3.00 Jan 18, 2006 page 407 of 1044

REJ09B0280-0300

13.3.8

VSYNCO Output

With the VSYNCO output, the meaning of the signal source to be selected and use or non-use of

modification varies according to the IVI signal source and the waveform required by external

circuitry. The meaning of the VSYNCO output in each mode is shown in table 13.10.

Table 13.10 Meaning of VSYNCO Output in Each Mode

Mode

IVI Signal

IVO Signal

Meaning of IVO Signal

No signal

VFBACKI

input

IVI signal (without fall

modification or IHI

synchronization)

VFBACKI input is output directly

IVI signal (without fall

modification, with IHI

synchronization)

Meaningless unless VFBACKI input is

synchronized with HFBACKI input

IVI signal (with fall

modification, without IHI

synchronization)

VFBACKI input fall is modified before output

IVI signal (with fall

modification and IHI

synchronization)

VFBACKI input fall is modified and signal is

synchronized with HFBACKI input before

output

IVG signal

Internal synchronization signal is output

S-on-G

mode or

composite

mode

PDC signal

IVI signal (without fall

modification or IHI

synchronization)

CSYNCI/HSYNCI input (composite

synchronization signal) vertical

synchronization signal part is separated

before output

IVI signal (without fall

modification, with IHI

synchronization)

CSYNCI/HSYNCI input (composite

synchronization signal) vertical

synchronization signal part is separated, and

signal is synchronized with CSYNCI/HSYNCI

input before output

IVI signal (with fall

modification, without IHI

synchronization)

CSYNCI/HSYNCI input (composite

synchronization signal) vertical

synchronization signal part is separated, and

fall is modified before output

IVI signal (with fall

modification and IHI

synchronization)

CSYNCI/HSYNCI input (composite

synchronization signal) vertical

synchronization signal part is separated, fall is

modified, and signal is synchronized with

CSYNCI/HSYNCI input before output

IVG signal

Internal synchronization signal is output

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