HD64F2149YV datasheet(438/1075 Pages) RENESAS

부품명	HD64F2149YV

상세설명	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

PDF	1075 Pages

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제조업체	RENESAS [Renesas Technology Corp]

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Section 14 Watchdog Timer (WDT)

Rev. 3.00 Jan 18, 2006 page 410 of 1044

REJ09B0280-0300

14.1.2

Block Diagram

Figures 14.1 (a) and (b) show block diagrams of WDT0 and WDT1.

Overflow

WOVI0

(interrupt request

signal)

Internal reset

signal*1

RESO signal*1

TCNT

TCSR

φ/2

φ/64

φ/128

φ/512

φ/2048

φ/8192

φ/32768

φ/131072

Clock

select

Internal clock

source

Bus

interface

Module bus

WDT0

Legend:

TCSR: Timer control/status register

TCNT: Timer counter

Internal NMI

interrupt request

signal*2

Interrupt

control

Reset

control

Notes: 1.

RESO pin output goes low when the internal reset signal is generated by overflow of TCNT

in either WDT0 or WDT1. The reset of the WDT that overflowed first takes precedence over

the internal reset signal.

2. The internal NMI interrupt request signal can be output independently by either WDT0 or

WDT1. The interrupt controller does not distinguish between NMI interrupt requests from

WDT0 and WDT1.

Figure 14.1 (a) Block Diagram of WDT0

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