HD64F2149YV datasheet(486/1075 Pages) RENESAS

486 / 1075 page

Section 15 Serial Communication Interface (SCI, IrDA)

Rev. 3.00 Jan 18, 2006 page 458 of 1044

REJ09B0280-0300

Clock

Either an internal clock generated by the built-in baud rate generator or an external clock input at

the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/

A bit in

SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table

15.9.

When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate

used.

When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The

frequency of the clock output in this case is equal to the bit rate, and the phase is such that the

rising edge of the clock is at the center of each transmit data bit, as shown in figure 15.3.

1 frame

0/1

Figure 15.3 Relation between Output Clock and Transfer Data Phase

(Asynchronous Mode)

Data Transfer Operations

SCI Initialization (Asynchronous Mode): Before transmitting and receiving data, first clear the

TE and RE bits in SCR to 0, then initialize the SCI as described below.

When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to

0 before making the change using the following procedure. When the TE bit is cleared to 0, the

TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not change the

contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR.

When an external clock is used the clock should not be stopped during operation, including

initialization, since operation is uncertain.

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