HD64F2149YV datasheet(560/1075 Pages) RENESAS

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Section 16 I

2C Bus Interface

Rev. 3.00 Jan 18, 2006 page 532 of 1044

REJ09B0280-0300

SDA

(master output)

SDA

(slave output)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bit 1

Bit 0

IRIC

ICDRS

ICDRR

RDRF

SCL

(master output)

SCL

(slave output)

Interrupt

request

generation

Interrupt

request

generation

Data 2

Data 1

[5] ICDR read

[5] IRIC clearance

User processing

Data 2

Data 1

[4]

Figure 16.10 Example of Slave Receive Mode Operation Timing (2) (MLS = ACKB = 0)

16.3.5

Slave Transmit Operation

In slave transmit mode, the slave device outputs the transmit data, while the master device outputs

the receive clock and returns an acknowledge signal. The transmission procedure and operations in

slave transmit mode are described below.

[1] Set the ICE bit in ICCR to 1. Set the MLS bit in ICMR and the MST and TRS bits in ICCR

according to the operating mode.

[2] When the slave address matches in the first frame following detection of the start condition,

the slave device drives SDA low at the 9th clock pulse and returns an acknowledge signal. At

the same time, the IRIC flag in ICCR is set to 1. If the IEIC bit in ICCR has been set to 1, an

interrupt request is sent to the CPU. .If the 8th data bit (R/

W) is 1, the TRS bit in ICCR is set

to 1, and the mode changes to slave transmit mode automatically. The TDRE internal flag is

set to 1. The slave device drives SCL low from the fall of the transmit clock until ICDR data is

written.

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