HD64F2149YV datasheet(564/1075 Pages) RENESAS

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Section 16 I

2C Bus Interface

Rev. 3.00 Jan 18, 2006 page 536 of 1044

REJ09B0280-0300

16.3.7

Automatic Switching from Formatless Mode to I

2C Bus Format

Setting the SW bit to 1 in DDCSWR enables formatless mode to be selected as the IIC0 operating

mode. Switching from formatless mode to the I

2C bus format (slave mode) is performed

automatically when a falling edge is detected on the SCL pin.

The following four preconditions are necessary for this operation:

• A common data pin (SDA) for formatless and I2C bus format operation

• Separate clock pins for formatless operation (VSYNCI) and I2C bus format operation (SCL)

• A fixed 1 level for the SCL pin during formatless operation (the SCL pin does not output a low

level)

• Settings of bits other than TRS in ICCR that allow I2C bus format operation

Automatic switching is performed from formatless mode to the I

2C bus format when the SW bit in

DDCSWR is automatically cleared to 0 on detection of a falling edge on the SCL pin. Switching

from the I

2C bus format to formatless mode is achieved by having software set the SW bit in

DDCSWR to 1.

In formatless mode, bits (such as MSL and TRS) that control the I

2C bus interface operating mode

must not be modified. When switching from the I

2C bus format to formatless mode, set the TRS

bit to 1 or clear it to 0 according to the transmit data (transmission or reception) in formatless

mode, then set the SW bit to 1. After automatic switching from formatless mode to the I

2C bus

format (slave mode), in order to wait for slave address reception, the TRS bit is automatically

cleared to 0.

If a falling edge is detected on the SCL pin during formatless operation, I

2C bus interface

operation is deferred until a stop condition is detected.

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