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HD64F2149YV 데이터시트(PDF) 643 Page - Renesas Technology Corp

부품명 HD64F2149YV
상세설명  Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
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제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

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Section 18B Host Interface LPC Interface (LPC)
Rev. 3.00 Jan 18, 2006 page 615 of 1044
REJ09B0280-0300
HICR0 Bit 3—LPC Software Shutdown Enable (SDWNE)
HICR1 Bit 3—LPC Software Shutdown Bit (SDWNB)
These bits control host interface shutdown. For details of the LPC shutdown function, and the
scope of initialization by an LPC reset and an LPC shutdown, see section 18B.3.4, Host Interface
Shutdown Function (LPCPD).
HICR0
Bit 3
SDWNE
Description
0
Normal state, LPC software shutdown setting enabled
(Initial value)
[Clearing conditions]
• Writing 0
• LPC hardware reset or LPC software reset
• LPC hardware shutdown release (rising edge of LPCPD signal)
1
LPC hardware shutdown state setting enabled
• Hardware shutdown state when LPCPD signal is low
[Setting condition]
• Writing 1 after reading SDWNE = 0
HICR1
Bit 3
SDWNB
Description
0
Normal state
(Initial value)
[Clearing conditions]
• Writing 0
• LPC hardware reset or LPC software reset
• LPC hardware shutdown
(falling edge of
LPCPD signal when SDWNE = 1)
• LPC hardware shutdown release
(rising edge of
LPCPD signal when SDWNE = 0)
1
LPC software shutdown state
[Setting condition]
• Writing 1 after reading SDWNB = 0



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