HD64F2149YV datasheet(644/1075 Pages) RENESAS

644 / 1075 page

Section 18B Host Interface LPC Interface (LPC)

Rev. 3.00 Jan 18, 2006 page 616 of 1044

REJ09B0280-0300

18B.2.3 Host Interface Control Registers 2 and 3 (HICR2, HICR3)

• HICR2

Bit

543

210

GA20

LRST

SDWN

ABRT

IBFIE3

IBFIE2

IBFIE1

ERRIE

Initial value

000

Slave Read/Write

R/(W)*

R/W

Host Read/Write

——

———

Note:

Only 0 can be written to bits 6 to 4, to clear the flags.

• HICR3

Bit

543

210

LFRAME CLKRUN SERIRQ LRESET LPCPD

PME

LSMI

LSCI

Initial value

000

Slave Read/Write

Host Read/Write

——

———

HICR2 and HICR3 contain flags and bits that control interrupts from the host interface (LPC)

module to the slave processor, and bits that monitor host interface pin states.

Bits 6 to 0 of HICR2 are initialized to H'00 by a reset and in hardware standby mode. The states of

the other bits are determined by the pin states.

HICR2 Bit 7—GA20 Pin Monitor (GA20)

HICR3 Bit 7—

LFRAME

LFRAME Pin Monitor (LFRAME)

HICR3 Bit 6—

CLKRUN

CLKRUN Pin Monitor (CLKRUN)

HICR3 Bit 5—SERIRQ Pin Monitor (SERIRQ)

HICR3 Bit 4—

LRESET

LRESET Pin Monitor (LRESET)

HICR3 Bit 3—

LPCPD

LPCPD Pin Monitor (LPCPD)

HICR3 Bit 2—

PME

PME Pin Monitor (PME)

HICR3 Bit 1—

LSMI

LSMI Pin Monitor (LSMI)

HICR3 Bit 0—LSCI Pin Monitor (LSCI)

These are pin state monitoring bits. The pin states can be monitored regardless of the host

interface operating state or the operating state of the functions that use pin multiplexing.

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