HD64F2149YV datasheet(678/1075 Pages) RENESAS

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Section 18B Host Interface LPC Interface (LPC)

Rev. 3.00 Jan 18, 2006 page 650 of 1044

REJ09B0280-0300

Slave CPU

Master CPU

ODR1 write

Write 1 to IRQ1E1

OBF1 = 0?

Yes

All bytes

transferred?

SERIRQ IRQ1 output

SERIRQ IRQ1

source clearance

Interrupt initiation

ODR1 read

Hardware operation

Software operation

Figure 18B.8 HIRQ Flowchart (Example of Channel 1)

18B.5

Usage Note

The following points should be noted when using the HIF : LPC.

(1) The host interface provides buffering of asynchronous data from the host processor and slave

processor, but an interface protocol that uses the flags in STR must be followed to avoid data

contention. For example, if the host and slave processor both try to access IDR or ODR at the

same time, the data will be corrupted. To prevent simultaneous accesses, IBF and OBF must be

used to allow access only to data for which writing has finished.

(2) Unlike the IDR and ODR registers, the transfer direction is not fixed for the two-way registers

(TWR). MWMF and SWMF are provided in STR to handle this situation. After writing to

TWR0, MWMF and SWMF must be used to confirm that the write authority for TWR1 to

TWR15 has been obtained.

(3) Table 18B.9 shows host address examples for corresponding registers when LADR3 = H'A24F

and LADR3 = H'3FD0.

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