HD64F2149YV datasheet(763/1075 Pages) RENESAS

부품명	HD64F2149YV

상세설명	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

PDF	1075 Pages

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제조업체	RENESAS [Renesas Technology Corp]

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763 / 1075 page

Section 23 Clock Pulse Generator

Rev. 3.00 Jan 18, 2006 page 735 of 1044

REJ09B0280-0300

Section 23 Clock Pulse Generator

23.1

Overview

The H8S/2169 and H8S/2149 have a built-in clock pulse generator (CPG) that generates the

system clock (

φ), the bus master clock, and internal clocks.

The clock pulse generator consists of an oscillator circuit, a duty-cycle adjustment circuit, clock

selection circuit, medium-speed clock divider, bus-master clock selection circuit, subclock input

circuit, and waveform shaping circuit.

23.1.1

Block Diagram

Figure 23.1 is a block diagram of the clock pulse generator.

EXTAL

XTAL

Oscillator

Duty-cycle

adjustment

circuit

EXCL

Subclock

input circuit

Waveform

shaping

circuit

Medium-speed

clock divider

System clock

φ pin

WDT1 count clock

Internal clock

To supporting

modules

Bus master clock

To CPU, DTC

φ/2 to φ/32

SUB

Bus-master

clock

selection

circuit

Clock

selection

circuit

Figure 23.1 Block Diagram of Clock Pulse Generator

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