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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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HD64F2149YV 데이터시트(PDF) 765 Page - Renesas Technology Corp |
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HD64F2149YV 데이터시트(HTML) 765 Page - Renesas Technology Corp |
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765 / 1075 page  Section 23 Clock Pulse Generator Rev. 3.00 Jan 18, 2006 page 737 of 1044 REJ09B0280-0300 Bit 2 Bit 1 Bit 0 SCK2 SCK1 SCK0 Description 0 0 0 Bus master is in high-speed mode (Initial value) 1 Medium-speed clock is φ/2 1 0 Medium-speed clock is φ/4 1 Medium-speed clock is φ/8 1 0 0 Medium-speed clock is φ/16 1 Medium-speed clock is φ/32 1— — 23.2.2 Low-Power Control Register (LPWRCR) 7 DTON 0 R/W R/W 6 LSON 0 R/W R/W 5 NESEL 0 R/W R/W 4 EXCLE 0 R/W R/W 3 — 0 R/W — 0 — 0 — — 2 — 0 — — 1 — 0 — — Bit Initial value Read/Write (H8S/2169) Read/Write (H8S/2149) LPWRCR is an 8-bit readable/writable register that performs power-down mode control. Only bit 4 is described here. For a description of the other bits, see section 24.2.2, Low-Power Control Register (LPWRCR). LPWRCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 4—Subclock Input Enable (EXCLE): Controls subclock input from the EXCL pin. Bit 4 EXCLE Description 0 Subclock input from EXCL pin is disabled (Initial value) 1 Subclock input from EXCL pin is enabled |
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