HD64F2149YV datasheet(786/1075 Pages) RENESAS

786 / 1075 page

Section 24 Power-Down State

Rev. 3.00 Jan 18, 2006 page 758 of 1044

REJ09B0280-0300

Bus master clock

φ,

supporting module

clock

Internal address

bus

Internal write signal

Medium-speed mode

SBYCR

Figure 24.2 Medium-Speed Mode Transition and Clearance Timing

24.4

Sleep Mode

24.4.1

Sleep Mode

If a SLEEP instruction is executed when the SSBY bit in SBYCR and the LSON bit in LPWRCR

are both cleared to 0, the CPU enters sleep mode. In sleep mode, CPU operation stops but the

contents of the CPU’s internal registers are retained. Other supporting modules do not stop.

24.4.2

Clearing Sleep Mode

Sleep mode is cleared by any interrupt, or with the

RES pin or STBY pin.

Clearing with an Interrupt: When an interrupt request signal is input, sleep mode is cleared and

interrupt exception handling is started. Sleep mode will not be cleared if interrupts are disabled, or

if interrupts other than NMI have been masked by the CPU.

Clearing with the

RES

RES Pin: When the RES pin is driven low, the reset state is entered. When the

RES pin is driven high after the prescribed reset input period, the CPU begins reset exception

handling.

Clearing with the

STBY

STBY Pin: When the STBY pin is driven low, a transition is made to hardware

standby mode.

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