HD64F2149YV datasheet(928/1075 Pages) RENESAS

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Appendix B Internal I/O Registers

Rev. 3.00 Jan 18, 2006 page 900 of 1044

REJ09B0280-0300

STR3—Status Register 3

H'FE32

HIF (LPC)

IBF3B

OBF3B

R/(W)*

MWMF

SWMF

R/(W)*

OBF3A

R/(W)*

DBU32

R/W

IBF3A

Bit

Initial value

Slave Read/Write

Host Read/Write

Note: * Only 0 can be written, to clear the flag.

Output data register full

[Clearing condition]

Host reads ODR using

I/O read cycle, or slave

writes 0 to OBF bit

[Setting condition]

Slave writes to ODR

Input data register full

User-defined bit

[Clearing condition]

Slave reads IDR

[Setting condition]

Host writes to IDR using I/O write cycle

Command/data

Input data register (IDR) contents are data

Input data register (IDR) contents are a command

Slave write mode flag

[Clearing condition]

Host reads TWR15 using I/O read cycle, or slave writes 0 to SWMF bit

[Setting condition]

Slave writes to TWR0 when MWMF = 0

Master write mode flag

[Clearing condition]

Slave reads TWR15

[Setting condition]

Host writes to TWR0 using I/O write cycle when SWMF = 0

Two-way register input data full

[Clearing condition]

Slave reads TWR15

[Setting condition]

Host writes to TWR15 using I/O write cycle

Two-way register output data full

[Clearing condition]

Host reads TWR15 using I/O read cycle, or slave writes 0 to OBF3B bit

[Setting condition]

Slave writes to TWR15

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