HD64F2149YV datasheet(197/1075 Pages) RENESAS

부품명	HD64F2149YV

상세설명	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

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Section 7 Data Transfer Controller

Rev. 3.00 Jan 18, 2006 page 169 of 1044

REJ09B0280-0300

7.1.3

Table 7.1 summarizes the DTC registers.

Table 7.1

DTC Registers

Name

Abbreviation

R/W

Initial Value

Address*

DTC mode register A

MRA

—*

Undefined

—*

DTC mode register B

MRB

—*

Undefined

—*

DTC source address register

SAR

—*

Undefined

—*

DTC destination address register

DAR

—*

Undefined

—*

DTC transfer count register A

CRA

—*

Undefined

—*

DTC transfer count register B

CRB

—*

Undefined

—*

DTC enable registers

DTCER

R/W

H'00

H'FEEE to H'FEF2

DTC vector register

DTVECR

R/W

H'00

H'FEF3

Module stop control register

MSTPCRH

R/W

H'3F

H'FF86

MSTPCRL

R/W

H'FF

H'FF87

Notes: 1. Lower 16 bits of the address.

2. Registers within the DTC cannot be read or written to directly.

3. Allocated to on-chip RAM addresses H'EC00 to H'EFFF as register information.

They cannot be located in external memory space.

When the DTC is used, do not clear the RAME bit in SYSCR to 0.

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