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HD64F2149YV 데이터시트(PDF) 219 Page - Renesas Technology Corp |
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HD64F2149YV 데이터시트(HTML) 219 Page - Renesas Technology Corp |
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219 / 1075 page ![]() Section 7 Data Transfer Controller Rev. 3.00 Jan 18, 2006 page 191 of 1044 REJ09B0280-0300 Read Write Read Write Address φ DTC activation request DTC request Data transfer Data transfer Transfer information write Transfer information write Transfer information read Transfer information read Vector read Figure 7.12 DTC Operation Timing (Chain Transfer) 7.3.10 Number of DTC Execution States Table 7.8 lists execution phases for a single DTC data transfer, and table 7.9 shows the number of states required for each execution phase. Table 7.8 DTC Execution Phases Mode Vector Read I Register Information Read/Write J Data Read K Data Write L Internal Operation M Normal 16 113 Repeat 1 6 1 1 3 Block transfer 1 6 N N 3 N: Block size (initial setting of CRAH and CRAL) |
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