HD64F2149YV datasheet(247/1075 Pages) RENESAS

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Section 8 I/O Ports

Rev. 3.00 Jan 18, 2006 page 219 of 1044

REJ09B0280-0300

8.4.3

Pin Functions in Each Mode

Mode 1, modes 2 and 3 (EXPE = 1): In mode 1, modes 2 and 3 (when EXPE = 1), port 3 pins

automatically function as data I/O pins. It is recommended that all the host interface enable bits

multiplexed as port 3 bits in single-chip mode (bit HI12E in SYSCR2 and bits LPC3E to LPC1E

in HICR0) be cleared to 0. The port 3 pin functions are shown in figure 8.10.

D15 (I/O)

D14 (I/O)

D13 (I/O)

D12 (I/O)

D11(I/O)

D10 (I/O)

D9 (I/O)

D8 (I/O)

Port 3

Figure 8.10 Port 3 Pin Functions (Modes 1 to 3 (EXPE = 1))

Modes 2 and 3 (EXPE = 0): In modes 2 and 3 (when EXPE = 0), port 3 functions as host

interface (LPC) I/O pins (SERIRQ, LCLK,

LRESET, LFRAME, LAD3 to LAD0), as host

interface (XBS) data bus I/O pins (HDB7 to HDB0), or as an I/O port. The priority order for pin

function settings is: LPC, XBS, I/O port.

When at least one of bits LPC3E to LPC1E is set to 1 in HICR0, port 3 functions as host interface

(LPC) I/O pins. Even in this state, it is recommended that the HI12E bit be cleared to 0 in

SYSCR2. P3DR and P3DDR should be cleared to H'00.

When the HI12E bit is set to 1 in SYSCR2, port 3 functions as the host interface (XBS) data bus.

In this case, P3DR and P3DDR should be cleared to H'00.

When bits LPC3E to LPC1E and HI12E are all cleared to 0, port 3 functions as an I/O port, and

input or output can be specified on a bit-by-bit basis. When a bit in P3DDR is set to 1, the

corresponding pin functions as an output port, and when cleared to 0, as an input port.

The port 3 pin functions are shown in figure 8.11.

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