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H8SX/1663 데이터시트(PDF) 646 Page - Renesas Technology Corp

부품명 H8SX/1663
상세설명  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
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제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

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Section 11 Programmable Pulse Generator (PPG)
Rev.1.00 Jun. 07, 2006 Page 594 of 1102
REJ09B0294-0100
11.4
Operation
Figure 11.2 shows a schematic diagram of the PPG. PPG pulse output is enabled when the
corresponding bits in NDER are set to 1. An initial output value is determined by its
corresponding PODR initial setting. When the compare match event specified by PCR occurs, the
corresponding NDR bit contents are transferred to PODR to update the output values. Sequential
output of data of up to 16 bits is possible by writing new output data to NDR before the next
compare match.
Output trigger signal
Pulse output pin
Internal data bus
Normal output/inverted output
C
PODR
QD
NDER
Q
NDR
QD
Figure 11.2 Schematic Diagram of PPG
11.4.1
Output Timing
If pulse output is enabled, the NDR contents are transferred to PODR and output when the
specified compare match event occurs. Figure 11.3 shows the timing of these operations for the
case of normal output in groups 2 and 3, triggered by compare match A.
TCNT
N
N + 1
P
φ
TGRA
N
Compare match
A signal
NDRH
mn
PODRH
PO8 to PO15
n
m
n
Figure 11.3 Timing of Transfer and Output of NDR Contents (Example)



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