H8SXSLASH1663M datasheet(481/1504 Pages) RENESAS

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Section 10 DMA Controller (DMAC)

Rev. 2.00 Sep. 24, 2008 Page 449 of 1468

REJ09B0412-0200

10.8

Interrupt Sources

The DMAC interrupt sources are a transfer end interrupt by the transfer counter and a transfer

escape end interrupt which is generated when a transfer is terminated before the transfer counter

reaches 0. Table 10.7 shows interrupt sources and priority.

Table 10.7

Interrupt Sources and Priority

Abbr.

Interrupt Sources

Priority

DMTEND0

Transfer end interrupt by channel 0 transfer counter

High

DMTEND1

Transfer end interrupt by channel 1 transfer counter

DMTEND2

Transfer end interrupt by channel 2 transfer counter

DMTEND3

Transfer end interrupt by channel 3 transfer counter

DMEEND0

Interrupt by channel 0 transfer size error

Interrupt by channel 0 repeat size end

Interrupt by channel 0 extended repeat area overflow on source address

Interrupt by channel 0 extended repeat area overflow on destination address

DMEEND1

Interrupt by channel 1 transfer size error

Interrupt by channel 1 repeat size end

Interrupt by channel 1 extended repeat area overflow on source address

Interrupt by channel 1 extended repeat area overflow on destination address

DMEEND2

Interrupt by channel 2 transfer size error

Interrupt by channel 2 repeat size end

Interrupt by channel 2 extended repeat area overflow on source address

Interrupt by channel 2 extended repeat area overflow on destination address

DMEEND3

Interrupt by channel 3 transfer size error

Interrupt by channel 3 repeat size end

Interrupt by channel 3 extended repeat area overflow on source address

Interrupt by channel 3 extended repeat area overflow on destination address

Low

Each interrupt is enabled or disabled by the DTIE and ESIE bits in DMDR for the corresponding

channel. A DMTEND interrupt is generated by the combination of the DTIF and DTIE bits in

DMDR. A DMEEND interrupt is generated by the combination of the ESIF and ESIE bits in

DMDR. The DMEEND interrupt sources are not distinguished. The priority among channels is

decided by the interrupt controller and it is shown in table 10.7. For details, see section 7, Interrupt

Controller.

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