H8SXSLASH1663M datasheet(484/1504 Pages) RENESAS

484 / 1504 page

Section 10 DMA Controller (DMAC)

Rev. 2.00 Sep. 24, 2008 Page 452 of 1468

REJ09B0412-0200

10.9

Usage Notes

1. DMAC Register Access During Operation

Except for clearing the DTE bit in DMDR, the settings for channels being transferred

(including waiting state) must not be changed. The register settings must be changed during

the transfer prohibited state.

2. Settings of Module Stop Function

The DMAC operation can be enabled or disabled by the module stop control register. The

DMAC is enabled by the initial value.

Setting bit MSTPA13 in MSTPCRA stops the clock supplied to the DMAC and the DMAC

enters the module stop state. However, when a transfer for a channel is enabled or when an

interrupt is being requested, bit MSTPA13 cannot be set to 1. Clear the DTE bit to 0, clear the

DTIF or DTIE bit in DMDR to 0, and then set bit MSTPA13.

When the clock is stopped, the DMAC registers cannot be accessed. However, the following

stop state, if necessary.

 TENDE bit in DMDR is 1 (the TEND signal output enabled)

 DACKE bit in DMDR is 1 (the DACK signal output enabled)

3. Activation by

DREQ Falling Edge

The

DREQ falling edge detection is synchronized with the DMAC internal operation.

A. Activation request waiting state: Waiting for detecting the

DREQ low level. A transition to

2. is made.

B. Transfer waiting state: Waiting for a DMAC transfer. A transition to 3. is made.

C. Transfer prohibited state: Waiting for detecting the

DREQ high level. A transition to 1. is

made.

After a DMAC transfer enabled, a transition to 1. is made. Therefore, the

DREQ signal is

sampled by low level detection at the first activation after a DMAC transfer enabled.

4. Acceptation of Activation Source

At the beginning of an activation source reception, a low level is detected regardless of the

setting of

DREQ falling edge or low level detection. Therefore, if the DREQ signal is driven

low before setting DMDR, the low level is received as a transfer request.

When the DMAC is activated, clear the

DREQ signal of the previous transfer.

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