H8SXSLASH1663M datasheet(608/1504 Pages) RENESAS

608 / 1504 page

Section 12 Data Transfer Controller (DTC)

Rev. 2.00 Sep. 24, 2008 Page 576 of 1468

REJ09B0412-0200

Table 12.3

Chain Transfer Conditions

1st Transfer

2nd Transfer

CHNE CHNS DISEL

Transfer

Counter*

CHNE CHNS DISEL

Transfer

Counter*

DTC Transfer



Not 0



Ends at 1st transfer



Ends at 1st transfer



Interrupt request to CPU



Not 0

Ends at 2nd transfer



Ends at 2nd transfer



Interrupt request to CPU

Not 0



Ends at 1st transfer



Not 0

Ends at 2nd transfer



Ends at 2nd transfer



Interrupt request to CPU

Not 0



Ends at 1st transfer

Interrupt request to CPU

Notes: 1. CRA in normal mode transfer, CRAL in repeat transfer mode, or CRB in block transfer

mode

2. When the contents of the CRAH is written to the CRAL in repeat transfer mode

12.5.1

Bus Cycle Division

When the transfer data size is word and the SAR and DAR values are not a multiple of 2, the bus

cycle is divided and the transfer data is read from or written to in bytes.

Table 12.4 shows the relationship among, SAR, DAR, transfer data size, bus cycle divisions, and

access data size. Figure 12.5 shows the bus cycle division example.

Table 12.4

Number of Bus Cycle Divisions and Access Size

Specified Data Size

SAR and DAR Values

Byte (B)

Word (W)

Longword (LW)

Address 4n

1 (B)

1 (W)

1 (LW)

Address 2n + 1

1 (B)

2 (B-B)

3 (B-W-B)

Address 4n + 2

1 (B)

1 (W)

2 (W-W)

H8SX/1663M 데이터시트(PDF) 608 Page - Renesas Technology Corp

H8SX/1663M 데이터시트(HTML) 608 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL