H8SXSLASH1663M datasheet(660/1504 Pages) RENESAS

660 / 1504 page

Section 13 I/O Ports

Rev. 2.00 Sep. 24, 2008 Page 628 of 1468

REJ09B0412-0200

(5)

PA3/

LLWR/LLB

The pin function is switched as shown below according to the combination of operating mode and

the EXPE bit, the bus controller register, and the PA3DDR bit settings.

Setting

Bus Controller

I/O Port

Module Name

Pin Function

LLB_OE*2

LLWR_OE*2

PA3DDR

LLB output*1



Bus controller

LLWR output*1

(initial value E)



PA3 output

I/O port

PA3 input

(initial value S)

[Legend]

Initial value E:

Initial value in external extended mode

Initial value S:

Initial value in single-chip mode

Notes: 1. Valid in external extended mode (EXPE = 1)

2. If the byte control SRAM space is accessed, this pin functions as the

LLB output;

otherwise, the

LLWR.

(6)

PA2/

BREQ/WAIT

The pin function is switched as shown below according to the combination of the bus controller

Setting

Bus Controller

I/O Port

Module Name

Pin Function

BCR_BRLE

BCR_WAITE

PA2DDR

BREQ input



Bus controller

WAIT input



PA2 output

I/O port

PA2 input

(initial value)

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