H8SXSLASH1663M datasheet(736/1504 Pages) RENESAS

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Section 14 16-Bit Timer Pulse Unit (TPU)

Rev. 2.00 Sep. 24, 2008 Page 704 of 1468

REJ09B0412-0200

14.3.3

Timer I/O Control Register (TIOR)

TIOR controls TGR. The TPU has eight TIOR registers, two each for channels 0 and 3, and one

each for channels 1, 2, 4, and 5. Care is required since TIOR is affected by the TMDR setting.

The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is

cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is

cleared to 0 is specified.

When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register

operates as a buffer register.

To designate the input capture pin in TIOR, the DDR bit and ICR bit for the corresponding pin

should be set to 0 and 1, respectively. For details, see section 13, I/O Ports.

• TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIOR_4, TIOR_5

IOB3

R/W

IOB2

R/W

IOB1

R/W

IOB0

R/W

IOA3

R/W

IOA2

R/W

IOA1

R/W

IOA0

R/W

Bit

Bit Name

Initial Value

R/W

• TIORL_0, TORL_3

IOD3

R/W

IOD2

R/W

IOD1

R/W

IOD0

R/W

IOC3

R/W

IOC2

R/W

IOC1

R/W

IOC0

R/W

Bit

Bit Name

Initial Value

R/W

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