전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

H8SX/1663M 데이터시트(PDF) 755 Page - Renesas Technology Corp

부품명 H8SX/1663M
상세설명  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663M 데이터시트(HTML) 755 Page - Renesas Technology Corp

Back Button H8SX/1663M Datasheet HTML 751Page - Renesas Technology Corp H8SX/1663M Datasheet HTML 752Page - Renesas Technology Corp H8SX/1663M Datasheet HTML 753Page - Renesas Technology Corp H8SX/1663M Datasheet HTML 754Page - Renesas Technology Corp H8SX/1663M Datasheet HTML 755Page - Renesas Technology Corp H8SX/1663M Datasheet HTML 756Page - Renesas Technology Corp H8SX/1663M Datasheet HTML 757Page - Renesas Technology Corp H8SX/1663M Datasheet HTML 758Page - Renesas Technology Corp H8SX/1663M Datasheet HTML 759Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 755 / 1504 page
background image
Section 14 16-Bit Timer Pulse Unit (TPU)
Rev. 2.00 Sep. 24, 2008 Page 723 of 1468
REJ09B0412-0200
Bit
Bit Name
Initial
value
R/W
Description
3
TGIED
0
R/W
TGR Interrupt Enable D
Enables/disables interrupt requests (TGID) by the TGFD bit
when the TGFD bit in TSR is set to 1 in channels 0 and 3.
In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as
0 and cannot be modified.
0: Interrupt requests (TGID) by TGFD bit disabled
1: Interrupt requests (TGID) by TGFD bit enabled
2
TGIEC
0
R/W
TGR Interrupt Enable C
Enables/disables interrupt requests (TGIC) by the TGFC bit
when the TGFC bit in TSR is set to 1 in channels 0 and 3.
In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as
0 and cannot be modified.
0: Interrupt requests (TGIC) by TGFC bit disabled
1: Interrupt requests (TGIC) by TGFC bit enabled
1
TGIEB
0
R/W
TGR Interrupt Enable B
Enables/disables interrupt requests (TGIB) by the TGFB bit
when the TGFB bit in TSR is set to 1.
0: Interrupt requests (TGIB) by TGFB bit disabled
1: Interrupt requests (TGIB) by TGFB bit enabled
0
TGIEA
0
R/W
TGR Interrupt Enable A
Enables/disables interrupt requests (TGIA) by the TGFA bit
when the TGFA bit in TSR is set to 1.
0: Interrupt requests (TGIA) by TGFA bit disabled
1: Interrupt requests (TGIA) by TGFA bit enabled
Note:
*
The bit 7 in TIER of unit 1 is a reserved bit. This bit is always read as 0 and the initial
value should not be changed.
14.3.5
Timer Status Register (TSR)
TSR indicates the status of each channel. The TPU has six TSR registers, one for each channel.
Bit
Bit Name
Initial Value
R/W
7
TCFD
1
R
6
1
5
TCFU
0
R/(W)*
4
TCFV
0
R/(W)*
3
TGFD
0
R/(W)*
2
TGFC
0
R/(W)*
1
TGFB
0
R/(W)*
0
TGFA
0
R/(W)*
Note: * Only 0 can be written to bits 5 to 0, to clear flags.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com