H8SXSLASH1663M datasheet(757/1504 Pages) RENESAS

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Section 14 16-Bit Timer Pulse Unit (TPU)

Rev. 2.00 Sep. 24, 2008 Page 725 of 1468

REJ09B0412-0200

Bit

Bit Name

Initial

value

R/W

Description

TGFD

R/(W)* Input Capture/Output Compare Flag D

Status flag that indicates the occurrence of TGRD input

capture or compare match in channels 0 and 3.

In channels 1, 2, 4, and 5, bit 3 is reserved. It is always

read as 0 and cannot be modified.

[Setting conditions]

• When TCNT = TGRD while TGRD is functioning as

output compare register

• When TCNT value is transferred to TGRD by input

capture signal while TGRD is functioning as input

capture register

[Clearing conditions]

• When DTC is activated by a TGID interrupt while the

DISEL bit in MRB of DTC is 0

• When 0 is written to TGFD after reading TGFD = 1

(When the CPU is used to clear this flag by writing 0

while the corresponding interrupt is enabled, be sure

to read the flag after writing 0 to it.)

TGFC

R/(W)* Input Capture/Output Compare Flag C

Status flag that indicates the occurrence of TGRC input

capture or compare match in channels 0 and 3.

In channels 1, 2, 4, and 5, bit 2 is reserved. It is always

read as 0 and cannot be modified.

[Setting conditions]

• When TCNT = TGRC while TGRC is functioning as

output compare register

• When TCNT value is transferred to TGRC by input

capture signal while TGRC is functioning as input

capture register

[Clearing conditions]

• When DTC is activated by a TGIC interrupt while the

DISEL bit in MRB of DTC is 0

• When 0 is written to TGFC after reading TGFC = 1

(When the CPU is used to clear this flag by writing 0

while the corresponding interrupt is enabled, be sure

to read the flag after writing 0 to it.)

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