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H8SX/1663M 데이터시트(PDF) 798 Page - Renesas Technology Corp |
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H8SX/1663M 데이터시트(HTML) 798 Page - Renesas Technology Corp |
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798 / 1504 page ![]() Section 14 16-Bit Timer Pulse Unit (TPU) Rev. 2.00 Sep. 24, 2008 Page 766 of 1468 REJ09B0412-0200 P φ Address Status flag Interrupt request signal Source address Destination address Period in which the next transfer request is masked T 1 T 2 DTC/DMAC read cycle DTC/DMAC write cycle T 1 T 2 Figure 14.44 Timing for Status Flag Clearing by DTC/DMAC Activation (1) P φ Address Status flag Interrupt request signal Source address Destination address Period of flag clearing Period of interrupt request signal clearing Period in which the next transfer request is masked DTC/DMAC read cycle DTC/DMAC write cycle Figure 14.45 Timing for Status Flag Clearing by DTC/DMAC Activation (2) |
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