H8SXSLASH1663M datasheet(896/1504 Pages) RENESAS

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Section 18 Watchdog Timer (WDT)

Rev. 2.00 Sep. 24, 2008 Page 864 of 1468

REJ09B0412-0200

(2)

Reading from TCNT, TCSR, and RSTCSR

These registers can be read from in the same way as other registers. For reading, TCSR is assigned

to address H'FFA4, TCNT to address H'FFA5, and RSTCSR to address H'FFA7.

18.6.2

Conflict between Timer Counter (TCNT) Write and Increment

If a TCNT clock pulse is generated during the T2 cycle of a TCNT write cycle, the write takes

priority and the timer counter is not incremented. Figure 18.5 shows this operation.

Address

Internal write signal

TCNT input clock

TCNT

TCNT write cycle

Counter write data

Figure 18.5 Conflict between TCNT Write and Increment

18.6.3

Changing Values of Bits CKS2 to CKS0

If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in

the incrementation. The watchdog timer must be stopped (by clearing the TME bit to 0) before the

values of bits CKS2 to CKS0 are changed.

18.6.4

Switching between Watchdog Timer Mode and Interval Timer Mode

If the timer mode is switched from watchdog timer mode to interval timer mode while the WDT is

operating, errors could occur in the incrementation. The watchdog timer must be stopped (by

clearing the TME bit to 0) before switching the timer mode.

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