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H8SX/1663M 데이터시트(PDF) 923 Page - Renesas Technology Corp

부품명 H8SX/1663M
상세설명  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

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Section 19 Serial Communication Interface (SCI, IrDA, CRC)
Rev. 2.00 Sep. 24, 2008 Page 891 of 1468
REJ09B0412-0200
Bit
Bit Name
Initial
Value
R/W
Description
5
ORER
0
R/(W)* Overrun Error
Indicates that an overrun error has occurred during
reception and the reception ends abnormally.
[Setting condition]
• When the next serial reception is completed while
RDRF = 1
In RDR, the receive data prior to an overrun error
occurrence is retained, but data received following the
overrun error occurrence is lost. When the ORER flag
is set to 1, subsequent serial reception cannot be
performed. Note that, in clocked synchronous mode,
serial transmission also cannot continue.
[Clearing condition]
• When 0 is written to ORER after reading ORER = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure
to read the flag after writing 0 to it.)
Even when the RE bit in SCR is cleared, the ORER
flag is not affected and retains its previous value.
4
ERS
0
R/(W)* Error Signal Status
[Setting condition]
• When a low error signal is sampled
[Clearing condition]
• When 0 is written to ERS after reading ERS = 1



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