H8SXSLASH1663M datasheet(116/1504 Pages) RENESAS

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Section 3 MCU Operating Modes

Rev. 2.00 Sep. 24, 2008 Page 84 of 1468

REJ09B0412-0200

Bit

Bit Name

Initial

Value

R/W

Descriptions



Undefined

Reserved

This bit is fixed at 1 in on-chip ROM enabled mode, and

0 in on-chip ROM disabled mode. This bit cannot be

changed.

EXPE

Undefined

R/W

External Bus Mode Enable

Selects external bus mode. In external extended mode,

this bit is fixed 1 and cannot be changed. In single-chip

mode, the initial value of this bit is 0, and can be read

from or written to when PCKJE = 0. Do not write to this

bit when PCKJE = 1*

When writing 0 to this bit after reading EXPE = 1, an

external bus cycle should not be executed.

The external bus cycle may be carried out in parallel

with the internal bus cycle depending on the setting of

the write data buffer function, refresh control function

and EXDMAC bus right release state and others.

0: External bus disabled

1: External bus enabled

RAME

R/W

RAM Enable

Enables or disables the on-chip RAM. This bit is

initialized when the reset state is released. Do not write

0 during access to the on-chip RAM.

0: On-chip RAM disabled

1: On-chip RAM enabled

7 to 2



All 0

R/W

Reserved

These bits are always read as 0. The write value should

always be 0.

DTCMD

R/W

DTC Mode Select

Selects DTC operating mode.

0: DTC is in full-address mode

1: DTC is in short address mode



R/W

Reserved

This bit is always read as 1. The write value should

always be 1.

Notes: 1. The initial value depends on the LSI initiation mode.

2. For details on the settings of the EXPE and PCJKE bits when the external address

space is in use, see section 13.3.12, Port Function Control Register D (PFCRD).

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